19.5.15

You are invited to attend a lecture

By

Godkin Andrey

Fabrication and Simulation of Electrostatically-formed Nanowire

Abstract

Silicon Nanowires (SiNWs) based field-effect transistors (FETs) are promising sensing devices and building

blocks for logic applications. SiNW based FETs are highly sensitive due to their high surface to volume ratio

and provide ultra-fast switching capabilities.

However, SiNWs FETs are incompatible with mass production mainly because of the complicated

fabrication methods and inhibiting integration into standard semiconductor processing.

The electrostatically-formed Nanowire (EFN) provides an alternative approach combining metal oxide

semiconductor (MOS) FET and JFET like transistors in one device where the conducting channel is

electrostatically tunable in its shape and diameter. Moreover, it is compatible with the standard CMOS

production process. Recently, the EFN was successfully applied as a gas sensor with parts per million (PPM)

sensitivity to ethanol vapor.

The main objective of this thesis was to simulate the fabrication of the second generation EFN conducted

by Tower Jazz, and simulate the electrical and sensing measurements. High-resolution functional imaging

and doping profiling was used to evaluate the process and the produced EFN device. It was found with

Kelvin probe force microscopy in combination with 3D electrostatic simulations that the EFN device is

tunable in its width from 46 to 16 nm.

In addition we demonstrate a threshold Logic with Multiple Gates EFN Transistor. It is a new concept for

integrated circuits, enabling more compact design blocks, reduced silicon chip area and hopefully smaller

power consumption.  In addition, we present the concept of a Multiple State EFN Transistor (MSET) that

uses the capability of the EFN to control the position of the channel by applying gate voltages, to navigate

from source to multiple drains. It is predicted to increase logic states from binary to more complex designs

and achieve lower power, switching speed and total footprint of future IC building blocks.

Thursday, May 19, 2015, at 15:00

Room 200, Wolfson building.