(EE Seminar: Percentile based cache decay prediction in LLC (last-level-cache
Speaker: Yuval Shekel
M.Sc. student under the supervision of Prof. Shlomo Weiss
Wednesday, February 12th 2020 at 15:30
Room 011, Kitot Bldg., Faculty of Engineering
Percentile based cache decay prediction in LLC (last-level-cache)
Abstract
Power dissipation is a highly limiting factor in CPUs ranging from low power to high-performance cores, limited to the cooling ability of the system.
Lower power dissipation can be directly translated to better battery life for low power devices or better performance at lower cost in the case of high performance cores.
Nowadays, leakage power is a bigger concern than ever due to decreasing transistor size and increasing cache sizes. Therefore, it makes sense to target cache leakage to achieve reduction in total dissipated power.
Typically, cache lines are brought to the cache, used several times then reside in ‘dead’ state, meaning they are not reused until evicted.
We propose an adaptive technique for early invalidation of last-level-cache (LLC) lines, not likely to be reused. The idea is to sample a small portion of the cache lines and generalize the program behavior for the entire cache. Compared to other methods, this one is more suited to large caches where per-cache-line behavior is too much overhead. The method is based on estimation of cache behavior statistics. In addition, it allows users to tune those statistics to trade-off performance to power depending on the application.
Our proposed adaptive technique is reducing 35% of the memory hierarchy power, on average, with negligible performance degradation.
